Design of CMOS Flip-Flops (SR, D, JK)

A flip-flop or latch is a circuit with two stable states, used to store state information. It is the basic storage element in sequential logic and a fundamental building block in digital electronics systems, including computers and communication devices.

Flip-flops and latches act as data storage elements for states, pulse counting, and synchronization of variably-timed input signals to a reference clock. Flip-flops can be transparent/opaque (latches) or clocked (synchronous, edge-triggered). Latches are level-sensitive, while flip-flops are edge-sensitive.

In sequential logic, the output depends on current inputs and previous states. Fig.1 shows a sequential circuit combining a combinational block and a memory element.

Fig.1: Sequential circuit consisting of a combinational logic block and a memory

Fig.2: Classification of logic circuits based on temporal behaviour

SR Flip-Flop

The SR latch can be implemented using two NAND gates. The circuit changes state when the Set (S) or Reset (R) input is pulled low. A NAND-based SR latch responds to active-low signals. The truth table and gate-level schematic are shown in Fig.3.

Fig.3: Circuit, Block Diagram & Truth Table of SR Latch

Fig.4: Circuit of SR Flip-Flop

Fig.5: Circuit of CMOS SR Flip-Flop

Fig.6: Timing diagram of CMOS SR Flip-Flop

JK Flip-Flop

The JK latch solves the "not allowed" input problem of SR latches by using feedback from outputs to inputs. Fig.7 shows an all-NAND JK latch with active-high inputs. J and K correspond to Set and Reset of an SR latch. If both inputs are 1 during the active clock, the latch toggles its state. Table.1 summarizes the JK flip-flop operation.

Fig.7: NAND implementation of the JK Flip-Flop

Table.1: Truth Table of the JK Flip-Flop

Fig.8: Circuit of CMOS JK Flip-Flop

D Flip-Flop

The D-latch stores a single logic level and acts as a 1-bit register. It has input D and outputs Q and Q’. It is implemented using a NOR-based SR latch: D connects to S and D’ to R through an inverter. When CLK is high, D is transmitted to Q; when CLK is low, the previous state is retained.

Fig.9: NOR implementation of the D Flip-Flop

Fig.10: Circuit of CMOS D Flip-Flop

Circuits / Block Diagram using S-Edit

Fig.11: CMOS SR Flip-Flop using S-Edit

Fig.12: CMOS JK Flip-Flop using S-Edit

Fig.13: CMOS D Flip-Flop using S-Edit

Programming (SPICE Command)

Extract SPICE code using T-Edit.

Graphs (W-Edit)

Simulate schematics and generate waveforms using W-Edit.

Conclusions

The transient response of SR, JK, and D Flip-Flops was studied using CMOS logic. Waveforms were obtained using W-Edit, and SPICE code was extracted using T-Edit. Observed waveforms match theoretical truth tables, validating the designs.

Further Reading

1. Introduction to Tanner EDA Tools
2. CMOS Logic Gates: Inverter, NAND, and NOR
3. EDA Tools and VHDL for VLSI Design
4. Layout of CMOS Inverter
5. Standard Cell Design in VLSI
6. Design of CMOS XOR/XNOR Gates
7. Design of CMOS Full Adder
8. Design of 8-bit Synchronous Counter
9. Design of 8-bit Bi-Directional Register
10. Design of a 12-bit CPU with Basic Instructions
11. VHDL Logical Function & CMOS Inverter
12. CMOS Layout Color Codes - IC Design Guide