Design of CMOS XOR/XNOR Gates

The semiconductor industry has experienced rapid integration of multimedia applications into mobile electronics, leading to very high integration density in CMOS VLSI. As operating frequencies increase, power consumption, speed, silicon area, and reliability become critical considerations.

The XOR-XNOR circuits are fundamental building blocks in arithmetic circuits (Full Adders, Multipliers), compressors, comparators, parity checkers, code converters, error-detecting/correcting codes, and phase detectors. Their performance directly impacts the complex circuits they are used in. Design goals include full output voltage swing, low power consumption, reduced transistor count, minimal delay, and simultaneous non-skewed outputs.

Static Logic (Static CMOS)

Static CMOS gates always provide a mechanism to drive outputs high or low.

• Pull-Up Network (PUN): Connects output to V_DD when output = 1.
• Pull-Down Network (PDN): Connects output to V_SS when output = 0.

The PUN and PDN are mutually exclusive; only one conducts at a time.

Fig.1: Complementary logic gate using PUN & PDN

Dynamic Logic

Dynamic logic uses a clock signal for combinational logic. It requires a minimum clock rate to ensure outputs are used before leakage. The PDN is similar to static CMOS. Operation occurs in two phases:

• Pre-charge (CLK=0): The output is charged to V_DD via the PMOS transistor; the PDN is off.
• Evaluation (CLK=1): The PMOS pre-charge transistor turns off, the NMOS evaluation transistor turns on. The output discharges conditionally based on inputs.

Fig.2: Dynamic gate operation (Pre-charge/Evaluation)

CMOS XOR & XNOR Gates

Static CMOS XOR/XNOR circuits use complementary PUN and PDN networks. They provide full output swing but require more transistors.

Logic expressions:

Z = A ⊕ B = (A + B)(A′ + B′)
Z′ = (A ⊕ B)′ = AB + A′B′
Z = (AB + A′B′)′ = A ⊕ B

Alternative realization of XOR/XNOR using CMOS is shown below:

Fig.3: XOR (a) & XNOR (b) gates using CMOS

Fig.4: Implementation of XOR & XNOR in one circuit

Fig.5: XNOR Circuit & Truth Table

Fig.6: XOR Circuit & Truth Table

Circuit Simulation / Block Diagram

Fig.7: XOR/XNOR Circuit using S-Edit (Transient Response)

Fig.8: Master Cell XOR/XNOR using S-Edit

Programming (SPICE Command)

SPICE code is extracted using T-Edit.

Graphs (W-Edit)

Simulate the schematic and generate waveforms corresponding to inputs using W-Edit.

Conclusions

In this experiment, the transient response of CMOS XOR/XNOR gates was studied. Waveforms were obtained using W-Edit, and SPICE code was extracted using T-Edit. The experiment demonstrates the design and analysis of XOR/XNOR gates in CMOS technology.