UGC-NET Electronic Science Question Paper With Answer Key and Full Explanation [June 2025]

  

 

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UGC-NET Electronic Science June 2025 Answers with Explanations

Explanations

1. For forming a p-type semiconductor, the dopant must be a trivalent impurity (three valence electrons) so that it creates acceptor levels and holes become the majority carriers. Among the given elements, boron (B) is a group-III element (trivalent). Arsenic (As) and phosphorus (P) are group-V (pentavalent) donors that produce n-type material, and germanium (Ge) is a group-IV element usually used as the semiconductor, not as an acceptor dopant. Hence, doping an intrinsic semiconductor with B produces a p-type semiconductor.

2. The ohmic resistance of a JFET at zero gate bias is given by the standard relation:

R_DS(on) = V_P / I_DSS

because in the ohmic (linear) region with V_GS = 0, the drain current is controlled by the pinch-off voltage and the saturation current.

Given:
V_P = 4 V,
I_DSS = 10 mA = 10 × 10^-3 A

Substituting:

R_DS(on) = 4 / (10 × 10^-3) = 4 / 0.01 = 400 Ω

Thus, the correct ohmic resistance is 400 Ω.

3. The Zener diode has breakdown voltage V_Z = 10 V and is in series with a resistor R = 820 Ω. The input supply varies from 20 V to 40 V. Maximum Zener current occurs at maximum input voltage when no load current is taken (worst case for Zener).

I_Z,max = (V_in,max − V_Z) / R

= (40 − 10) / 820 = 30 / 820 A

= 0.0366 A = 36.6 mA

Therefore, the maximum current through the Zener diode is 36.6 mA.

4. For a silicon diode, the saturation current approximately doubles for every 10°C rise in temperature. The temperature increases from 25°C to 95°C.

ΔT = 95 − 25 = 70°C

Number of 10°C steps:

70 / 10 = 7

So, the multiplication factor is:

2⁷ = 128

Initial saturation current is I_S1 = 5 nA. Thus,

I_S2 = I_S1 × 128 = 5 × 128 = 640 nA

Hence, the saturation current at 95°C is 640 nA.

5. In λ-based layout design rules for VLSI, the commonly adopted minimum width and spacing. Correct answer is 4*lambda

6. In standard CMOS inverter consisting of a PMOS at the top with its source connected to V_DD and an NMOS transistor at the bottom with its source connected to ground, their gates are tied together to form the input V_in, and their drains are tied together to form the output V_out. Under steady-state condition (PMOS ON, NMOS OFF), V_out ≈ V_DD. Under complementary condition (PMOS OFF, NMOS ON), V_out ≈ 0. Thus, the correct CMOS inverter schematic is identified accordingly.

7. A graph of C_j versus V shows a straight line when the junction doping profile is linearly graded. For a linearly graded junction, the depletion width varies with voltage such that the capacitance–voltage relationship becomes linear when plotted as 1/C_j³ vs V. Shallow or abrupt profiles do not produce linearity, and a quadratic grading produces curvature, not a straight line.

8. The thermodynamic concentration relation follows Arrhenius law, where concentration decreases exponentially with activation energy. The correct physical expression is:

N_v = A · exp(−E_a / kT)

The negative sign in the exponent is essential because higher activation energy reduces equilibrium dopant concentration. Any option with a positive exponent or reciprocal A is physically incorrect.

9. The number of octaves between two frequencies is obtained using logarithmic relations:

log₁₀2 = 0.301

Octaves = log₂(f₂/f₁) = log₁₀(f₂/f₁) / log₁₀2

= log₁₀(f₂/f₁) / 0.301

10. A two-port network is symmetric if its input and output characteristics remain identical when ports are interchanged. In Z-parameters, this requires:

Z₁₁ = Z₂₂

Reciprocity requires:

Z₁₂ = Z₂₁

Thus, a symmetric network satisfies both conditions.

11. Maximum power transfer occurs when the load impedance equals the complex conjugate of the internal impedance. If the network has impedance:

Z = R + jX

Then the load must be:

Z_L = R − jX

This cancels the reactive term and ensures maximum power transfer.

12. In this circuit, the state variables are capacitor voltage v_c and inductor current i_L.

At node A, KCL gives:

i = i_c + i_L

= C (dv_c/dt) + i_L

Thus,

dv_c/dt = (1/C)(i − i_L)

For the inductor-resistor branch, KVL gives:

v_c = L (di_L/dt) + R i_L

So,

di_L/dt = (1/L)v_c − (R/L)i_L

This yields the state-space representation.

13

Phase-Locked Loop (PLL) Locking Condition

In a PLL, the divided VCO output must match the input reference frequency for the PLL to remain in the locked state. The block diagram shows a "÷4 Counter", meaning the VCO output is divided by 4 before being fed back to the phase-frequency detector.

Therefore, the locking condition is f_in = f_out / 4
With the given input reference frequency f_in = 40 MHz,
The locked VCO output frequency must be four times this value:
f_out = 4 × 40 MHz = 160 MHz

14

Op-Amp & MOSFET Circuit Analysis

The non-inverting input of the ideal op-amp is fixed at 2 V, so the op-amp forces the inverting input (node connected to the 4 kΩ resistor and MOSFET gate circuit) to also be at exactly 2 V. The current through the 4 kΩ resistor is determined by the voltage difference between 3 V and the forced 2 V at the inverting input.

Thus, the drain current is:
I_D = (3 - 2) / 4 kΩ = 1/4 mA = 0.25 mA

This same current must flow through the 1 kΩ resistor connected to V_o because the MOSFET is in saturation and the loop forces the same drain current.
Therefore: V_o = I_D × 1 kΩ
V_o = 0.25 mA × 1000 = 0.25 V

15

Closed-Loop Gain of Non-Inverting Amplifier

The circuit is a non-inverting amplifier with feedback resistor R_f = 20 kΩ and grounding resistor R_g = 10 kΩ.

The feedback factor is β = R_g / (R_g + R_f) = 10 / 30 = 1/3
The open-loop gain is limited to A = 15 V/V.
The closed-loop gain A_CL with finite open-loop gain is:
A_CL = A / (1 + Aβ)

Substituting values:
A_CL = 15 / (1 + 15 × 1/3) = 15 / (1 + 5) = 15 / 6 = 2.5 V/V

Thus the closed-loop gain of the circuit is 2.5 V/V.

16

Op-Amp Bandwidth and Dominant Pole

An open-loop gain of 100 dB corresponds to a linear gain of A₀ = 10^100/20 = 10⁵. For a single-pole op-amp, the unity-gain bandwidth (UGB) equals the gain-bandwidth product.

f_UGB = A₀ × f_p (where f_p is the dominant-pole bandwidth).
Given f_UGB = 1 GHz, the open-loop bandwidth is:
f_p = f_UGB / A₀ = 10⁹ / 10⁵ = 10⁴ Hz = 10 kHz

17

Demultiplexer Tree Implementation

To implement a 1-to-256 demultiplexer using 1-to-4 demultiplexers, we cascade stages in a 4-ary tree. Each 1-to-4 demux gives 4 outputs.

We need 4ⁿ = 256
Writing 256 as a power of 4: 256 = 2⁸ = 4⁴
So we need 4 stages.
Number of 1-to-4 demux ICs: 1 + 4 + 4² + 4³ = 1 + 4 + 16 + 64 = 85
Hence, 85 such demultiplexers are required.

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18

Transmission-Gate Logic (XOR Function)

The circuit is a transmission-gate implementation of a logic function. The control signals are B and B.

When B = 0, upper switch connects input A to output: Y = A.
When B = 1, lower switch connects A to output: Y = A.
Combining these: Y = BA + BA, which is exactly the XOR function Y = A ⊕ B.

19

Multiplexer Feedback Circuit

The circuit is a 2-to-1 multiplexer whose one data input is the external signal A and the other data input is the output Y fed back. The select line is "Sel".

When "Sel" = 1, MUX selects A: Y = A.
When "Sel" = 0, MUX selects the feedback input: Y = Y_prev.

Sequential Circuits & Multiplexers

so Y keeps its previous value (Y_new = Y_old). This "load when Sel = 1, hold when Sel = 0" behavior is exactly that of a level-sensitive latch, not a simple combinational gate or an edge-triggered flip-flop.

20: In the given circuit, the D input of the first flip-flop is formed by XOR-ing its own output Q with logic '1'. For a D flip-flop, Q_next = D on each active clock edge; when D = Q ⊕ 1 = Q', the flip-flop toggles its state on every clock edge, so the output frequency is half the clock frequency.

With a 10 kHz clock, the first flip-flop thus produces a 5 kHz square wave at its Q output. The second flip-flop, clocked by the same 10 kHz and driven appropriately, does not further change this basic divide-by-2 action at the observed output node, so the waveform at Q has frequency 5 kHz.

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Microprocessor Architecture

21: The 8051 is an 8-bit microcontroller, meaning it processes 8-bit data and has 8-bit wide ALU and data paths. Architecturally, it uses separate program and data memory spaces (program memory addressed via PSEN, data memory via read/write strobes), which is the defining feature of a Harvard architecture. It is neither 16-bit nor 32-bit, and it does not follow the single shared-memory Von-Neumann model. Therefore the correct description is "8-bit Harvard architecture".

22: TYPE 4 interrupt in 8085 is the restart interrupt RST 4. RST 4 is triggered by the overflow flag (V flag). Therefore, TYPE 4 corresponds to the overflow interrupt.

23: The Intel 8086 microprocessor is fabricated using HMOS technology. Its transistor count is approximately 29,000 transistors. The other options represent counts of much newer or older processors, not 8086.

24: Instruction AAA (ASCII Adjust after Addition) is specifically used after adding two unpacked BCD/ASCII-coded decimal digits in register AL. It examines the lower nibble of AL and the auxiliary carry flag; if the result is not a valid BCD digit (0-9), it adds 6 to AL and adjusts AH accordingly. Thus, AAA is meant to adjust the ASCII/BCD content of AL after an ADD instruction, which corresponds exactly to "Adjust ASCII after addition."

Vector Calculus & EM Fields

25: The vector is:

A̅ = 3y²z² â_x + 4x³z² â_y + 3z²y² â_z

Divergence is: ∇ · A̅ = ∂Ax/∂x + ∂Ay/∂y + ∂Az/∂z

Compute each term: ∂/∂x(3y²z²) = 0 (no x in expression) ∂/∂y(4x³z²) = 0 (no y in expression) ∂/∂z(3z²y²) = 6zy²

∇ · A̅ = 6zy²

26: Electric flux density D is defined as: D = εE. D has units of coulombs per square meter. Therefore the correct is C/m².

27: Velocity of a uniform plane wave in free space is:

v = 1 / √(μ₀ε₀) This is the speed of light in vacuum (≈ 3 × 10⁸ m/s).

28: The characteristic impedance of free space is:

η₀ = √(μ₀/ε₀) ≈ 377 Ω

Angle Modulation

29: The angle-modulated signal is:

x_c(t) = 10 cos [ (10⁸ π)t + 5 sin (2π (10³)t) ]

The phase deviation term is 5 sin (·).