Harvard vs Von Neumann Architecture

1. Basic Idea

Feature	Von Neumann	Harvard
Memory for instructions and data	Same memory	Separate memories
Bus system	One shared bus	Separate buses
Can fetch instruction and data together?	No	Yes
Speed	Slower	Faster
Complexity	Simpler	More complex

2. Von Neumann Architecture

In this design, instructions and data are stored in the same memory. The CPU uses the same bus for both instruction fetch and data transfer.

Example

Address	Content
100	Instruction: ADD
101	Data = 5
102	Data = 7

CPU operations:

1. Fetch instruction from address 100
2. Fetch data from address 101
3. Fetch data from address 102
4. Perform addition

Timing Calculation

Fetch instruction = 1 cycle
Fetch data = 1 cycle each
Execute = 1 cycle

Total cycles = 1 + 1 + 1 + 1 = 4 cycles

Diagram

        +--------+
        |  CPU   |
        +--------+
            |
      Shared Bus
            |
   +----------------+
   | Instructions   |
   | and Data       |
   +----------------+
    

3. Harvard Architecture

In Harvard architecture, instructions and data are stored separately. The CPU has separate buses for instruction and data access.

Example

Instruction Memory

Address	Instruction
100	ADD

Data Memory

Address	Data
50	5
51	7

The CPU can fetch instruction and data simultaneously.

Timing Calculation

Instruction fetch = 1 cycle
Data fetch = 1 cycle
Execute = 1 cycle

Total cycles ≈ 2 cycles

Speedup = 4 / 2 = 2× faster

Diagram

           +--------+
           |  CPU   |
           +--------+
           /        \
 Instruction     Data
    Bus            Bus
     |              |
+----------+   +----------+
| Program  |   |   Data   |
| Memory   |   |  Memory  |
+----------+   +----------+
    

4. Mathematical Comparison

Let:

Ti = Instruction fetch time
Td = Data fetch time

Von Neumann

TVN = Ti + Td

Harvard

TH = max(Ti, Td)

Example:

Ti = 5ns
Td = 5ns

Von Neumann: 5 + 5 = 10ns

Harvard: max(5,5) = 5ns

Harvard is approximately 2× faster.

5. Real-World Usage

Architecture	Used In
Von Neumann	PCs, laptops, Intel CPUs, AMD CPUs
Harvard	Microcontrollers, DSPs, Arduino AVR, PIC

6. Summary

Point	Von Neumann	Harvard
Memory	Shared	Separate
Cost	Lower	Higher
Speed	Slower	Faster
Design	Simpler	Complex
Bottleneck	Present	Reduced