Harvard vs Von Neumann Architecture
1. Basic Idea
| Feature | Von Neumann | Harvard |
|---|---|---|
| Memory for instructions and data | Same memory | Separate memories |
| Bus system | One shared bus | Separate buses |
| Can fetch instruction and data together? | No | Yes |
| Speed | Slower | Faster |
| Complexity | Simpler | More complex |
2. Von Neumann Architecture
In this design, instructions and data are stored in the same memory. The CPU uses the same bus for both instruction fetch and data transfer.
Example
| Address | Content |
|---|---|
| 100 | Instruction: ADD |
| 101 | Data = 5 |
| 102 | Data = 7 |
CPU operations:
- Fetch instruction from address 100
- Fetch data from address 101
- Fetch data from address 102
- Perform addition
Timing Calculation
Fetch data = 1 cycle each
Execute = 1 cycle
Diagram
+--------+
| CPU |
+--------+
|
Shared Bus
|
+----------------+
| Instructions |
| and Data |
+----------------+
3. Harvard Architecture
In Harvard architecture, instructions and data are stored separately. The CPU has separate buses for instruction and data access.
Example
Instruction Memory
| Address | Instruction |
|---|---|
| 100 | ADD |
Data Memory
| Address | Data |
|---|---|
| 50 | 5 |
| 51 | 7 |
The CPU can fetch instruction and data simultaneously.
Timing Calculation
Data fetch = 1 cycle
Execute = 1 cycle
Diagram
+--------+
| CPU |
+--------+
/ \
Instruction Data
Bus Bus
| |
+----------+ +----------+
| Program | | Data |
| Memory | | Memory |
+----------+ +----------+
4. Mathematical Comparison
Let:
Td = Data fetch time
Von Neumann
Harvard
Example:
Td = 5ns
5. Real-World Usage
| Architecture | Used In |
|---|---|
| Von Neumann | PCs, laptops, Intel CPUs, AMD CPUs |
| Harvard | Microcontrollers, DSPs, Arduino AVR, PIC |
6. Summary
| Point | Von Neumann | Harvard |
|---|---|---|
| Memory | Shared | Separate |
| Cost | Lower | Higher |
| Speed | Slower | Faster |
| Design | Simpler | Complex |
| Bottleneck | Present | Reduced |
7. The Von Neumann Bottleneck
The Von Neumann Bottleneck is a limitation that occurs because the CPU and memory are separated and share a single bus. Since the CPU is much faster than the memory, it often sits idle while waiting for data to arrive.
- Impact: Even with a fast processor, the overall speed is capped by the bus throughput.
- Solution: This led to the development of Caches (L1, L2, L3) and the Harvard Architecture to provide parallel access paths.
8. Modern CPUs: Modified Harvard Architecture
Did you know that modern PCs (Intel/AMD) use both? This is called Modified Harvard Architecture.
- At the Cache level: They use Harvard Architecture (Separate L1 Instruction and L1 Data caches) for extreme speed.
- At the Main Memory level: They use Von Neumann Architecture (RAM stores both programs and data) to keep costs low and simplify memory management.
Advantages and Disadvantages
Von Neumann
Pros: Flexible use of memory; cheaper to build; simpler OS design.
Cons: Serial execution (bottleneck); slower for heavy processing.
Harvard
Pros: High speed; supports "Pipelining"; no bottleneck between code and data.
Cons: More physical pins required on the CPU; complex to manufacture; unused program memory cannot be used for data.
Frequently Asked Questions (FAQ)
Is Arduino Harvard or Von Neumann?
Most Arduinos (like the Uno using ATmega328P) use Harvard Architecture. The Flash memory for code is separate from the SRAM for data.
Why is Von Neumann still used if Harvard is faster?
Because it is more flexible and cheaper. In a PC, you might want to use 8GB of RAM for a game today and 8GB for a database tomorrow. Von Neumann allows this flexibility; Harvard does not.