A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure...
Q. A shift-left Shift Register (SR) and a D flip-flop are connected
to a synchronized clock as shown in the figure. Assume that the
SR and D flip-flops are initially cleared and the XOR gate has
no propagation delay.
Which of the following options gives the correct binary
representation (b7b6b5b4b3b2b1b0)
of the content of the shift register immediately after the
5th clock transition (positive edge)?
Step-by-step Solution
Step 1: Initial Conditions
- Shift register (SR) =
00000000 - D flip-flop output Q = 0
- One input of the XOR gate is connected to logic 1.
Therefore, the XOR output is:
DSR = Q ⊕ 1
= 0 ⊕ 1 = 1
Step 2: Understand the Circuit
- The shift register shifts left at every positive clock edge.
- The XOR output provides the serial input to the shift register.
- The D flip-flop stores the outgoing bit b7.
- Initially, all register bits are zero.
Step 3: Track the Shift Register
The register shifts left and receives a serial input of 1 during the first five clock transitions.
| Clock | Register Content (b₇ ... b₀) |
|---|---|
| Initial | 00000000 |
| 1st | 00000001 |
| 2nd | 00000011 |
| 3rd | 00000111 |
| 4th | 00001111 |
| 5th | 00011111 |
Answer A
Immediately after the 5th positive clock edge:
(b₇ b₆ b₅ b₄ b₃ b₂ b₁ b₀)
00011111
Summary
At every positive clock edge, the shift register and D flip-flop update simultaneously using their input values immediately before that clock edge.