Skip to main content

UGC NET Electronic Science December 2024 Question Paper with Answer Key & Detailed Solutions


Home / UGC NET PYQ / June 2025 Solved

UGC NET Electronic Science December 2024 Question Paper with Answer Key and Full Explanations

📥 Download Question Paper (PDF)

Q.1
Answer: Option (3)

Q.2
Answer: Option (3)

Solution

1. JMP SHORT LABEL
Intrasegment (within the same code segment).
Direct jump.
❌ Not intersegment indirect.
2. JMP 5000H:2000H
Intersegment (far jump because both CS and IP are specified).
Direct jump (address is explicitly given).
❌ Not indirect.
3. JMP [2000H]
The destination address is taken from memory location 2000H.
This is indirect.
In 8086, a far indirect jump can use a memory operand containing both IP and CS (depending on operand size), making it an intersegment indirect jump.
✅ Correct answer.
4. JMP [BX]
Indirect jump through memory addressed by BX.
Usually intrasegment (near indirect jump).
❌ Not intersegment.

Q.3
Answer: Option (3)

Q.4
Answer: Option (4)

For inverting OP-AMP

V0 = -Rf/Rin * Vin

or, V0 = -10/(16/8) * 2 = -10 V

Q.5
Answer: Option (3)


6. The feedback network used in Colpitts oscillator is given below:

20 mH C₂ C₁ 4 pF

The value of \(C_2\) and feedback factor '\(\beta\)' for oscillating frequency of 1 MHz is:

1. 0.8 pF, 0.2
2. 4 pF, 0.9
3. 1.8 pF, 0.45
4. 2.2 pF, 0.9
Answer: 3
Solution:

The oscillating frequency \(f_0\) of a Colpitts oscillator is given by:

\(f_0 = \frac{1}{2\pi\sqrt{L_{eq}C_{eq}}}\)

where \(L_{eq}\) is the total inductance and \(C_{eq}\) is the equivalent capacitance.

In this case, \(L = 20 \text{ mH}\) and \(C_1 = 4 \text{ pF}\).

The equivalent capacitance for two capacitors in series is \(C_{eq} = \frac{C_1 C_2}{C_1 + C_2}\).

The given frequency is \(f_0 = 1 \text{ MHz}\).

Substituting the values:

\(1 \times 10^6 = \frac{1}{2\pi\sqrt{20 \times 10^{-3} \times \frac{4 \times 10^{-12} \times C_2}{4 \times 10^{-12} + C_2}}}\)

Solving for \(C_2\):

Squaring both sides and rearranging, we get:

\((2\pi f_0)^2 L = \frac{C_1 C_2}{C_1 + C_2}\)

\(\frac{C_1 C_2}{C_1 + C_2} = \frac{1}{(2\pi \times 10^6)^2 \times 20 \times 10^{-3}}\)

Let's calculate the right-hand side value first:

\(\frac{1}{(2\pi \times 10^6)^2 \times 20 \times 10^{-3}} \approx \frac{1}{(39.48 \times 10^{12}) \times 20 \times 10^{-3}} \approx \frac{1}{789.6 \times 10^9} \approx 1.266 \times 10^{-12} \text{ F} = 1.266 \text{ pF}\)

So, \(\frac{4 \times C_2}{4 + C_2} = 1.266\) (where \(C_2\) is in pF)

\(4 C_2 = 1.266 (4 + C_2)\)

\(4 C_2 = 5.064 + 1.266 C_2\)

\(2.734 C_2 = 5.064\)

\(C_2 = \frac{5.064}{2.734} \approx 1.85 \text{ pF}\)

This is closest to 1.8 pF.

The feedback factor \(\beta\) is given by \(\beta = \frac{C_2}{C_1}\).

\(\beta = \frac{1.8 \text{ pF}}{4 \text{ pF}} = 0.45\)

Therefore, the correct option is 1.8 pF and 0.45.

Q.7
Answer: Option (4)

Q.8
Answer: Option (3)

Q.9
Answer: Option (3)

Q.10
Answer: Option (4)

Q.11
Answer: Option (3)

Solution Hint: 20 * 0.8 = 16KW ; 16 / 0.85 = 18.82

Q.12
Answer: Option (2)

Solution Hint: E = V/d; j = epsilon * dE/dt

Q.13
Answer: Option (3)

Q.14
Answer: Option (3)

Q.15
Answer: Option (2)

Solution Hint: 1 / (2 * pi * r)

Q.16
Answer: Option (3)

Solution Hint: 1 / RC

Q.17
Answer: Option (3)

Q.18
Answer: Option (2)

Solution Hint: Ftotal = (F1 + (F2 - 1)/G)

Q.19
Answer: Option (3)

Q.20
Answer: Option (3)

Solution Hint: V(t) = V0(1 - e^(-t/RC))

Q.21: Oscillator Matching
Answer: Option (4)

C. LC Oscillator → I: Uses inductors and capacitors for feedback and resonance. It is mainly used for radio frequency (RF) applications like Hartley and Colpitts oscillators.

D. Crystal Oscillator → II: Uses a quartz crystal for high stability. Crystals have sharp resonance and thus are used where high frequency stability is required.

Matching is: A-III, B-IV, C-I, D-II.

Q.22
Answer: Option (1)

To find the open-loop transfer function, we trace the forward and feedback paths step-by-step.

Forward Path: G1G2
Feedback Loops: G1H1, G2H2, and the nested loop G1G2H3 + G1G2H1H2.

Full transfer function becomes:

G1G2 / (G1H1 + G2H2 + G1G2H3 + G1G2H1H2)

Q.23: Rise Time Calculation

Bandwidth = 10 MHz

tr = 0.35 / Bandwidth
tr = 0.35 / (10 × 106)
tr = 35 ns.

Q.24: Effective Mass (mn*/m0)
Answer: Option (4)

  • InSb: 0.014 | GaAs: 0.067 | AlAs: 0.15 | BN: 0.20 | GaP: 0.34

Ascending Order: InSb < GaAs < AlAs < BN < GaP (C, A, D, B, E).

Q.25: RTD Temperature Calculation
Answer: Option (1)

Given: R0 = 100 Ω, R = 150 Ω, α = 0.004/°C, T0 = 25°C

150 = 100(1 + 0.004(T - 25))
1.5 = 1 + 0.004(T - 25)
0.5 / 0.004 = T - 25
125 = T - 25 → T = 150°C

Q.26: SCR Conduction State
Answer: Option (2)

In an SCR (P-N-P-N) during conduction:

  • J1 & J3: Forward biased.
  • J2: Initially reverse biased, switches to forward bias once triggered.

Correct Condition: J1 and J3 forward biased, J2 reverse biased (blocking mode boundary).

Q.27: Priority of interrupts in 8086
Answer: Option (B)

Order from highest to lowest:

  • Reset (B) - absolute highest, restarts processor
  • Internal Interrupts (A) - traps and exceptions
  • Software Interrupts (D) - user-defined INT instructions
  • Non-maskable Interrupt (E) - cannot be disabled
  • Hardware Interrupt (C) - INTR, triggered externally

Correct descending order: B > A > D > E > C.

Q.28: LVDT Application
Answer: Option (2)

An LVDT (Linear Variable Differential Transformer) measures displacement by providing a variable output voltage in proportion to the position of a movable core.

Q.29: Monolayer Formation Time
Answer: Option (2)

Formula: t = Ns / P

Computing values for each case:

(A) Ns / P = 2.64 × 1014 / 1 = 2.64 × 1014
(B) Ns / P = 5.28 × 1014 / 10-1 = 5.28 × 1015
(C) Ns / P = 2.64 × 1014 / 10-8 = 2.64 × 1022
(D) Ns / P = 7.29 × 1014 / 1 = 7.29 × 1014

Ascending order of time: A, D, B, C.

Q.30: Ampere's Circuital Law
Answer: Option (3)

∮ H • dL = Ienclosed

Relates the line integral of magnetic field intensity H to the total current enclosed, based on Maxwell's equations.

Q.31: Inverse Fourier Transform
Answer: Option (4)

Substitute X(ω) = δ(ω - ω0) into the inversion integral:

x(t) = (1 / 2π) ∫ δ(ω - ω0)ejωt dω = (1 / 2π) ejω0t

Q.32: Laplace & System Response
Answer: Option (2)

System Equation: s2Y(s) + 3sY(s) + 2Y(s) = X(s)

H(s) = 1 / (s2 + 3s + 2) = 1 / ((s + 1)(s + 2))

For unit step input X(s) = 1/s, applying partial fractions:

Y(s) = 1/2s - 1/(s+1) + 1/(2(s+2))

Inverse Laplace: y(t) = (1/2 - e-t + (1/2)e-2t) u(t)

Q.33: Conductivity Computation
Answer: Option (3)

Formula: σ = ωε tan δ

ω = 2π × 108 ≈ 6.28 × 108
ε = 18 × 8.85 × 10-12 = 1.593 × 10-10
σ = (6.28e8) × (1.593e-10) × (9.85e-3) = 9.86 × 10-4 S/m

Q.34: System Cascade Properties
Answer: Option (3)

  • Statement A: Cascade of linear systems is linear (True).
  • Statement C: Cascade of causal systems is causal (True).
  • Statement D: Cascade of time-invariant systems is time-invariant (True).
If the individual blocks are non-linear, the overall system is usually non-linear, but it is not a fixed rule. For example, if h1(x)=log⁡(x) and h2(x)=e^x, both are non-linear, but their cascade e^log⁡(x)=x is linear. Therefore, this statement B is not universally true. (FALSE)

Q.35: Barkhausen Criterion
Answer: Option (2)

  • Statement A: Loop gain magnitude must be 1 (True).
  • Statement D: Total phase shift must be 0° or 360° (True).

Q.36: Error Constants

Answer: Option (2)

Evaluating Position Error Constant (Kp) for G(s) = 50 / [(1+0.15s)(s+10)]:

Kp = lims→0 G(s) = 50 / 10 = 5

Q.37: 8086 Control Flags

Answer: Option (1)

Machine control flags include: Direction Flag (DF), Trap Flag (TF), and Interrupt Flag (IF).

Q.38: Communication Systems

Answer: Option (2)

  • Shannon-Hartley: Capacity formula.
  • Huffman Coding: Source coding/Lossless compression.
  • OFDM: 4G/5G Physical Layer.

Q.39. Option (4)


Q.40: 8051 Stack Pointer (SP)

Answer: Option (4)

SP is an 8-bit register. It is initialized to 07H on reset. Data is stored at 08H on the first PUSH.

Q.41: Z-Transform ROC

Answer: Option (3)

  • Causal finite → All Z except 0.
  • Anticausal finite → All Z except infinity.
  • Causal infinite → |z| > r.

Order: A, D, B, C.

Q.42: Inverse Transducers

Answer: Option (4)

Piezoelectric crystals act as inverse transducers by converting electrical voltage into mechanical motion (vibration).

Q.43: Gauge Factor (GF) Analysis

Answer: Option (2)

Formula: GF = (Δl / l) ⋅ (1 + 2 ⋅ ΔD / D)

(A) GF = (1/24)(1 + 2*0.02/1.5) = 0.0428
(B) GF = (1/15)(1 + 2*0.02/1.5) = 0.0685
(D) GF = (2/20)(1 + 2*0.02/0.5) = 0.1080
(C) GF = (2/15)(1 + 2*0.01/0.5) = 0.1387

Ascending Order: A, B, D, C.

Q.44: Common-Source MOSFET Amplifier

Parameters: gm = 2 mA/V, rd = 10 kΩ, RD = 50 kΩ.

Total output resistance (Rout):

Rout = (rd ⋅ RD) / (rd + RD) = (10 × 50) / 60 = 8.33 kΩ

Voltage gain (Av):

Av = -gm ⋅ (rd || RD) = -2 × 10⁻³ × 8333.33 = -16.66

Q.45: Digital Logic Fan-out (74HC driving 74LS)

For logic LOW: Max inputs = IOL(max) / IIL(max) = 4 mA / 0.4 mA = 10

For logic HIGH: Max inputs = IOH(max) / IIH(max) = 4 mA / 20 μA = 200

Since 10 is the limiting case (LOW state), the fan-out is 10.

Q.46: Pinch-off Voltage (VP) Calculation
Answer: Option (3)

VP = (q ND d2) / (2ε)

Given: q = 1.6e-19, ND = 2e24 m⁻³, d = 40e-9 m, ε = 1.089e-10.

VP = (1.6e-19 ⋅ 2e24 ⋅ (40e-9)²) / (2 ⋅ 1.089e-10) ≈ 2.35 V.

Q.47: 3-bit Asynchronous Binary Counter
Answer: Option (3)

  • A. Correct: Pulse 5 high phase indicates FF2 and FF3 in hold mode.
  • B. Incorrect: FF3 toggles every 4 pulses, not on the 6th pulse edge.
  • C. Correct: During pulse 5 high, FF1 is ready to toggle while FF3 holds.
  • D. Incorrect: FF2 does not toggle on pulse 4 edge.

Correct statements: A and C only.

Q.48: Multivibrator & Circuit Matching
Answer: Option (2)

  • A. Monostable → III (Delay circuit)
  • B. Bistable → IV (Flip-flop/Counter)
  • C. Clamping → II (DC Level shifter)
  • D. Schmitt trigger → I (Noise removal/Hysteresis)

Q.49: P-N Junction Diode Statements
Answer: (2)

A. True: Equilibrium requires a flat Fermi level.
B. False: Depletion width WD depends on doping (WD ∝ √(1/N)).
C. True: 1/C² vs V plot yields doping density and built-in potential.
D. False: Avalanche breakdown (> 6V) has a positive temperature coefficient.

Correct statements: A and C only.

Q.50: BJT Circuit Voltages
Answer: Option (1)

Given: β=45, VBE=0.7V, RB=100k, RC=1.2k, VEE=-9V.

VB = VE + VBE = -9 + 0.7 = -8.3 V

IB = 8.3 / 100k = 83 μA | IC = 45 ⋅ 83μA = 3.735 mA

VC = 0 - (3.735mA ⋅ 1.2k) = -4.48 V

Q.51: Scaling Principles
Answer: Option (3)

Statements A, C, and D are correct. Scaling is systematic (A), miniaturization alters characteristics (C), and supply voltages are often kept constant for I/O compatibility (D).

Q.52: Modulation Power Requirements
Answer: 3 (Correct order: A, B, C, D, E)

Order of decreasing power: FM > AM > DSB-SC >VSB-SC> SSB-SC. SSB-SC is the most efficient.

Q.53: Optical Fiber Windows
Answer: 4 (A, B, E)

Standard windows: 850 nm (First), 1310 nm (Second), and 1550 nm (Third).

Q.54: Microscope & Spectroscopy Matching
Answer: Option (2)

Matchings: A → II (SEM-Surface), B → I (XRD-Crystal), C → III (TEM-Internal), D → IV (EDS-Composition).

Q.55: Power Device Matching
Answer: Option (4)

A → II (DIAC-Bidirectional Diode), B → IV (TRIAC-AC Control), C → I (IGBT-Bipolar Mode), D → III (SCR-Unidirectional).

Q.56: Superheterodyne Receiver
Answer: Option (4)

A. True: Mixer stage generates sum and difference frequencies.
C. True: IF amplifier operates at a fixed frequency for better gain/selectivity.

Q.57: 8086 Physical Address Calculation
Answer: Option (2)

Physical Address = (Segment × 10H) + Offset

(1005H × 10H) + 5555H = 10050H + 5555H = 155A5H

Q.58: D-to-A Converter Weights
Answer: Option (3)

Weight is inversely proportional to resistance: P (1k) > R (2k) > Q (4k) > S (8k).
Order: C, D, A, B.

Q.59: Antenna Gain Ranking

Answer: Option (3)

Decreasing order: Horn (D) >Yagi-Uda (C) > Dipole (B) > Monopole (A)

Typical gains: Yagi (~10dBi), Horn (~15dBi), Monopole (lowest gain), Dipole (~2dBi).

Q.60: MOS Fabrication Steps
Answer: Option (1)

Correct order: B, A, C, D. (Thick oxide growth → Gate oxide/PSG deposition → n-type doping → Planarization/Metallization).

Q.61: Silicon Growth (FZ vs CZ)
Answer: Option (3)

FZ process offers lower contamination compared to CZ because it does not use a crucible.

Q.62: Cellular Channel Splitting
Answer: Option (3)

Logic: 12 macrocells × 3 microcells per macrocell = 36 total cells.
36 cells × 10 channels = 360 channels.

Q.63: Hall Voltage Calculation (n-type Ge)
Answer: Option (3)

vd = μn ⋅ Ex = 0.38 ⋅ 500 = 190 m/s

VH = vd ⋅ Bz ⋅ w = 190 ⋅ 0.1 ⋅ 4e-3 = 76 mV

Direction: -Y direction (electrons accumulate on -y side).

Q.64: Transducer Definitions
Answer: Option (4)

Statements A, B, and C are true. Current-carrying coils in magnetic fields (motors) are inverse transducers, not primary sensors.

Q.65: Thin Film Vacuum Environment
Answer: Option (1)

Vacuum increases the mean free path of atoms, allowing them to reach the substrate without collisions.

Q.66: MOSFET Transconductance (gm)
Answer: Option (4)

In saturation:

gm = dID / dVgs = 2ID / (Vgs - Vth)

Q.67: 8051 Port 3 Pins
Answer: Option (2)

Port 3 matching: P3.0 (RxD), P3.1 (TxD), P3.2 (INT0), P3.3 (INT1), P3.4 (T0), P3.5 (T1).

8051 Port 3 Alternate Functions

Pin Function Description
P3.0RXDSerial Data Input
P3.1TXDSerial Data Output
P3.2INT0External Interrupt 0
P3.3INT1External Interrupt 1
P3.4T0Timer 0 Input
P3.5T1Timer 1 Input
P3.6WRData Memory Write
P3.7RDData Memory Read

Matching: A-III (P3.0-RXD), B-I (P3.3-INT1), C-IV (P3.6-WR), D-II (P3.7-RD).

Q.68: Hertzian Dipole Radiated Power
Answer: Option (1)

Prad = 40π2 I02 • (dl / λ)2

Where I0 is peak current, dl is length, and λ is wavelength.

Q.69: 8086 ADD and DAA Instructions
Answer: Option (1)

Initial: AL = 73H, CL = 29H.

ADD AL, CL: 73H + 29H = 9CH (CF=0)

DAA Adjustment: Lower nibble (C > 9) → add 6: 9C + 6 = A2. Upper nibble (A > 9) → add 60: A2 + 60 = 102H.

Final result: AL = 02H, CF = 1.

Q.70: Entropy Calculation
Answer: Option (1)

H = -∑ pi log2(pi)

If p=1, H = -1 • log2(1) = 0. (No uncertainty).

Q.71: Root Type Analysis for Parameter K
Answer: Option (3)

Given S = -1 ± √(1 - K)

A. 0 < K < 1 → Roots are Real & Distinct (IV)
B. K = 0 → Roots are S1=0, S2=-2 (III)
C. K = 1 → Roots are Real & Equal (I)
D. K > 1 → Roots are Complex Conjugates (II)

Matching: A-IV, B-III, C-I, D-II.

Q.72: Gunn Diode Characteristics
Answer: Option (1)

B. True: Operates on hot electron transfer to higher energy valleys.
C. True: Relies on bulk negative resistance, not junctions.

Q.73: Bandgap Descending Order (0 K)
Answer: Option (2)

Values: Diamond (5.5 eV) > GaN (3.4 eV) > AlP (2.45 eV) > CdSe (1.84 eV) > PbTe (0.32 eV).
Order: B, D, A, C, E.

Q.74: Lattice Network Z-Parameters
Answer: Option (3)

Lattice with series arms 4 Ω and diagonal arms 8 Ω.

Z11 = Z22 = (4+8) || (8+4) = 12 || 12 = 6 Ω

Z12 = Z21 = ½(Zdiag - Zseries) = ½(8 - 4) = 2 Ω

Q.75: Switch and Logic Gate Circuit
Answer: Option (3)

AND gate output = A. OR gate output = Y.
If S1 is Open (1) and S2 is Closed (0):
AND(1,0) → A = 0 (Low). OR(1,0,0) → Y = 1 (High).

Q.76: TTL Speed-Power Product (Descending)
Answer: Option (2)

Order: 74 Standard (100pJ) > 74S (60pJ) > 74LS (18pJ) > 74ALS (4pJ).
Order: B, C, A, D.

Q.77: Amplifier Conduction Angles
Answer: Option (3)

Order: Class A (360°) > Class AB (180-360°) > Class B (180°) > Class C (<180 br=""> Order: B, A, D, C.

Q.78: Nyquist Stability Criterion
Answer: Option (1)

A. True: Critical point is -1 + j0.
C. True: Stable if no zeros (closed-loop poles) in the right-half S plane.

Q.79: Solar Cell Open-Circuit Voltage
Answer: Option (4)

Voc = (kT/q) ln(IL/Is + 1)

Voc = 0.025875 ⋅ ln(108) ≈ 0.48 V

Q.80: Antenna Property Matching
Answer: Option (3)

A-IV (λ/2 Dipole: 73 Ω), B-I (Wire: l > λ/2), C-II (Reflector: Parabolic), D-III (Arrays: High Directivity).

Q.81: K-map Function Minimization
Answer: Option (3)

Y = ∑m(7, 9, 10, 11, 12, 13, 14, 15).
Filling the K-map for variables AB and CD allows for grouping and term reduction.

K-map Grouping

  • Group 1 (m12-15): AB = 11 → term = AB
  • Group 2 (m10, 11, 14, 15): A=1, D=1 → term = AD
  • Group 3 (m9, 11): A=1, B=0, D=1 → term = A·B'·D
  • Group 4 (m7, 15): B=1, C=1, D=1 → term = BCD
  • Group 5 (m10, 14): A=1, C=1, D=0 → term = AC

Simplified Boolean expression: Y = AB + AC + AD + BCD

Correct Answer: Option 3.

Q.82: Metal-Semiconductor Systems
Answer: Option (3)

Statement A: (Correct) Covalent surfaces have high surface states near the neutral level (Eg/3).

Statement C: (Correct) Optical dielectric constant dependence on wavelength is similar for Si, Ge, and GaAs.

Note: Statement B is an oversimplification for semiconductors, and Statement D is false because higher barrier height increases resistance.

Q.83: Brillouin Zone Symmetry (FCC/Diamond)
Answer: Option (3)

  • A. Γ (Center): Degeneracy = 1 (II)
  • B. X (100): Degeneracy = 6 (I)
  • C. K (110): Degeneracy = 12 (IV)
  • D. L (111): Degeneracy = 8 (III)

Q.84: 8051 Instruction Trace
Answer: Option (4)

MOV A, #0CDH → A = 11001101
RR A (Rotate Right) → A = 11100110
CPL A (Complement) → A = 00011001
SWAP A (Nibble Swap) → A = 10010001 = 91H

Q.85: 7445 Decoder LED Current
Answer: Option (2)

Supply = 5V, VLED = 1.2V, R = 1kΩ.

VR = 5 - 1.2 = 3.8V

I = VR / R = 3.8V / 1kΩ = 3.8 mA

Q.86: Reduction-Projection Lithography
Answer: Option (1)

Resolution (R) = K1(λ / NA)

Depth of Focus (DOF) = K2(λ / NA2)

Q.87: Reflex Klystron Characteristics
Answer: Option (1)

  • A. True: It is a single cavity klystron.
  • C. True: Bunching parameter has a negative sign.
  • E. True: Space charge effects are neglected in basic analysis.

Q.88: Peripheral IC Matching
Answer: Option (4)

  • A. 8259 → IV (Interrupt Controller)
  • B. 8251 → III (USART)
  • C. 8279 → II (Keyboard/Display)
  • D. 8254 → I (Timer)

Q.89: N-channel FET Statements
Answer: Option (3)

B. True: Larger transconductance than P-channel due to electron mobility.

D. True: Electrons provide larger mobility than holes used in P-channels.

Q.90: Communication System Matching
Answer: Option (1)

  • A. FM → III (Carson's Rule)
  • B. DSB-SC → I (Costas Receiver)
  • C. PIN → II (Photodetector)
  • D. Optical → IV (WDM)

Q.91: 4x1 Multiplexer Output
Answer: Option (4)

Select Lines: S1=A=0, S0=B=1 (Binary 01).

The MUX selects input I1. Given I1 = C̅.
Result: F = C̅.

Q.92: 4-bit Even Parity Checker
Answer: Option (3)

Output C = x ⊕ y ⊕ z ⊕ P

For Option 3: x=1, y=0, z=1, P=1.
C = 1 ⊕ 0 ⊕ 1 ⊕ 1 = 1. (Correct).

Q.93: Mealy State Diagram Analysis
Answer: Option (4)

Analyzing transitions (Input/Output):

From state d, if input = 0, the transition goes to b with output 0. (Matches Option 4).

Q.94: 74ALS164 Shift Register (6th Pulse)
Answer: Option (3)

Initial: 00000000. Input A·B = 1.
After 6 clocks (shifting in 1s): Q7 to Q0 = 00111111.
Represented as 11111100 (Option 3).

Q.95: PLD Logic Output
Answer: Option (1)

Connections for O1 OR gate:
AND1 = A̅B | AND2 = AB̅.
Result: O1 = A̅B + AB̅ (XOR Logic).

Q.96: Lossless Line Phase Constant
Answer: Option (2)

β = ω√(LC)

Q.97: Quarter-Wavelength (λ/4) Line
Answer: Option (3)

The normalized impedance inverts: Zin = Z02 / ZL.

Q.98: VSWR Definition
Answer: Option (1)

VSWR = |V|max / |V|min

Q.99: Characteristic Impedance (Z0)
Answer: Option (3)

Z0 = √((R + jωL) / (G + jωC))

Q.100: Transmission Line Modeling
Answer: Option (1)

Transmission lines use the Distributed Method (R, L, G, C parameters over infinitesimally small lengths).



Contact Us

Name

Email *

Message *

Popular Posts

CMOS Logic Gates: Inverter, NAND, and NOR

CMOS Logic Gates: Inverter, NAND, and NOR Complementary metal–oxide–semiconductor (CMOS) technology forms the backbone of modern digital IC design. Patented by Frank Wanlass in 1963 ( US patent 3,356,858 ), CMOS enables low-power, high-speed, and noise-immune logic circuits. CMOS gates, including inverters, NAND, and NOR, are widely used in both large-scale and small-scale integrated circuits due to their efficiency and versatility. CMOS Inverter A CMOS inverter consists of a complementary pair of PMOS and NMOS transistors. The PMOS transistor connects to the supply voltage V DD , while the NMOS connects to ground. The input voltage V IN controls both gates, and the output voltage V OUT is taken from the connected drains. CMOS inverters are highly energy-efficient and produce minimal heat due to their comple...

UGC NET Electronic Science Previous Year Question Papers with Solutions

Download Papers and Solutions Exam Pattern Preparation Tips FAQs More Home / Engineering & Other Exams / UGC NET 2026 PYQ 📊 Exam Highlights: Electronic Science (88) Feature Details Junior Research Fellowship (JRF) ₹37,000 + HRA per month Eligibility M.Sc/M.Tech in Electronics (55%) Validity of Certificate JRF (3 Years) | Lectureship (Lifetime) 📥 Download UGC NET Electronics PDFs Complete collection of previous year question papers, answer keys and explanations for Subject Code 88. Start Downloading 📂 View All Question Papers June 2026 - Question Paper Download PDF June 202...

Design of CMOS Flip-Flops (SR, D, JK)

Design of CMOS Flip-Flops (SR, D, JK) A flip-flop or latch is a circuit with two stable states, used to store state information. It is the basic storage element in sequential logic and a fundamental building block in digital electronics systems, including computers and communication devices. Flip-flops and latches act as data storage elements for states, pulse counting, and synchronization of variably-timed input signals to a reference clock. Flip-flops can be transparent/opaque (latches) or clocked (synchronous, edge-triggered). Latches are level-sensitive, while flip-flops are edge-sensitive. In sequential logic, the output depends on current inputs and previous states. Fig.1 shows a sequential circuit combining a combinational block and a memory element. ...

Linear vs Circular Convolution

Linear vs Circular Convolution Linear convolution vs circular convolution Linear convolution (what nature does) If: x[n] = transmitted signal h[n] = channel impulse response (multipath) Then the received signal is: y[n] = x[n] * h[n] This means: Past symbols spill into future symbols Causes inter-symbol interference (ISI) DFT of y[n] is not a simple product Circular convolution (what DFT assumes) The DFT assumes periodic signals : y[n] = x[n] ⊛ h[n], where indices wrap around modulo N Only under circular convolution does the DFT satisfy: Y[k] = X[k] · H[k] This is what enables one-tap frequency-domain equalization . What happens in the real channel (linear convolution) The channel performs linear convolution: y[n] = Σ l=0 Lh−1 h[l] x[n-l] But because: CP absorbs the “spillover” Receiver discards CP before DFT The useful part of the received symbol becomes: y[n] = Σ l=0 Lh−1 h[l] x[(n-l) mod N] Modulo inde...

Flat vs Frequency Selective Online Simulator

Flat vs Frequency Selective Online Simulator Channel Type Without Fading Flat Fading Multipaths Nakagami m SNR(dB) Run Simulation Input Signal Signal After Fading Constellation Diagram BER vs SNR Explore Advanced Flat vs Frequency-Selective Fading Simulator Want to see these equations in action? Visualize it. Launch Simulator Tool Interactive Rayleigh Fading Simulator Want to see Rayleigh fading in action? Visualize it. Launch Simulator Tool Return to DSP Simulations Main Page →

MUSIC Algorithm Explained (with MATLAB + Simulator)

Practical Implementation of the MUSIC Algorithm The focus is on how the algorithm works computationally , not just theory, and it explains the denominator (a H E n E n H a) mathematically and intuitively. 1. Introduction The MUSIC (Multiple Signal Classification) algorithm is a high-resolution method used in signal processing and array processing to estimate the Direction of Arrival (DOA) of signals received by a sensor array. Unlike classical beamforming methods, MUSIC uses eigenvector decomposition of the covariance matrix to separate the signal subspace and noise subspace , allowing it to achieve much higher angular resolution. In practical implementations, MUSIC works by: Simulating or collecting array signals Computing the covariance matrix Performing eigenvalue decomposition Separating signal and noise subspaces Scanning possible angles using a steering vector Constructing a pseudo-spectrum where peaks indicate signal directions 2. Signal Mo...

Constellation Diagrams of ASK, PSK, and FSK (with MATLAB Code + Simulator)

Constellation Diagrams: ASK, FSK, and PSK Comprehensive guide to signal space representation, including interactive simulators and MATLAB implementations. 📘 Overview 🧮 Simulator ⚖️ Theory 📈 Q-function 📚 Resources BASK Modulation Transmits one of two signals: 0 or $\sqrt{E_b}$, representing binary 0 and 1. Simple but sensitive to noise. BFSK Modulation Transmits one of two signals: $\sqrt{E_b}$ on the Y-axis or $\sqrt{E_b}$ on the X-axis. These are orthogonal signals. BPSK Modulation Transmits $+\sqrt{E_b}$ or $-\sqrt{E_b}$ (antipodal signaling). Most efficient binary scheme. ...

Design of CMOS XOR/XNOR Gates

Design of CMOS XOR/XNOR Gates The semiconductor industry has experienced rapid integration of multimedia applications into mobile electronics, leading to very high integration density in CMOS VLSI. As operating frequencies increase, power consumption, speed, silicon area, and reliability become critical considerations. The XOR-XNOR circuits are fundamental building blocks in arithmetic circuits (Full Adders, Multipliers), compressors, comparators, parity checkers, code converters, error-detecting/correcting codes, and phase detectors. Their performance directly impacts the complex circuits they are used in. Design goals include full output voltage swing, low power consumption, reduced transistor count, minimal delay, and simultaneous non-skewed outputs. Static Logic (Static CMOS) Stat...