Standard Cell Design in VLSI

Standard Cell Design

Designing complex logic functions from scratch is often expensive and time-consuming. The standard cell methodology provides a more efficient approach. A standard cell library contains pre-designed logic gates such as NOT, AND, OR, NAND, NOR, XOR, Flip-Flop, and Buffer, which can be interconnected to create complex circuits. This hierarchical design approach reduces design time and cost.

Diagram showing contents of a typical standard cell library including logic gates and components — Fig.1. Contents of a Typical Standard Cell Library

Characterization of Standard Cells

Standard Cell Based VLSI Design Flow

Front End:
- System specification and architecture
- HDL coding & behavioural simulation
- Synthesis & gate-level simulation
Back End:
- Placement and routing
- DRC (Design Rule Check)
- LVS (Layout vs Schematic)
- Dynamic simulation and static analysis

Types of Cells in a Library

Standard Core Cells
Input/Output (I/O) Cells

Design & Verification Steps

Schematic Design
Layout Design
Layout versus Schematic (LVS)
Extraction from Layout (Device & Parasitic Extraction)
Antenna Effect and Antenna Rules
Library Characterization (Timing, Voltage, Temperature, Process Variation)
Cell Characterization (Propagation Delay, Rise/Fall Time, Ring Oscillator, Power Analysis)
Reliability & Noise Characterization (Crosstalk, Electromigration, GOI, Channel Hot Carrier)
Interconnect Delay Modelling (RC, Elmore, Transmission Line)

Circuits / Block Diagram

CMOS inverter circuit schematic — Fig.2. Circuit Diagram of CMOS Inverter

Layout design of CMOS inverter — Fig.3. Layout of CMOS Inverter

Simulation results waveform of CMOS inverter — Fig.4. Simulation Results of CMOS Inverter

Input and output waveform showing rise and fall times — Fig.5. Input & Output Waveforms showing Rise and Fall Times

Three stage ring oscillator circuit diagram — Fig.6. Three Stage Ring Oscillator Circuit

Output waveform of three stage ring oscillator — Fig.7. Three Stage Ring Oscillator’s Output Waveform

Observations & Data

The standard cell design characterization includes schematic creation, layout design, simulation, LVS, DRC verification, extraction, propagation delay measurement, and rise & fall time analysis. Tanner EDA tools (S-Edit, L-Edit, W-Edit, T-Edit) provide full support for these steps.

Conclusions

A standard cell library design involves defining the logic functions, accurately simulating and modeling electrical characteristics of gates, and exporting all characterization data in a standard format. Using Tanner EDA tools, the CMOS Inverter and Ring Oscillator circuits were successfully designed, simulated, and verified.

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