Rise Time in Logic Families
Definition
The rise time (tr) of a logic family is the time taken for a signal to change from 10% to 90% of its final voltage value when transitioning from logic LOW (0) to logic HIGH (1).
Waveform Diagram
Voltage
5V | _________
| /
4.5V|----------* ← 90%
| /
| /
| /
0.5V|------* ← 10%
| /
0V |____/________________ Time
Rise time is measured between the points marked at 10% (0.5 V) and 90% (4.5 V).
Comparison of Logic Families
| Logic Family | Typical Rise Time | Speed | Notes |
|---|---|---|---|
| TTL (Transistor-Transistor Logic) | ~5–15 ns | Medium | Widely used, moderate power |
| CMOS (Older) | ~20–50 ns | Slower | Very low power |
| CMOS (Modern) | ~1–5 ns | Fast | Used in modern ICs |
| ECL (Emitter-Coupled Logic) | ~0.5–2 ns | Very Fast | High power consumption |
Numerical Example
Consider a logic gate where the output changes from 0 V to 5 V:
- 10% of 5 V = 0.5 V
- 90% of 5 V = 4.5 V
If the signal reaches:
- 0.5 V at 2 ns
- 4.5 V at 10 ns
Rise Time (tr) = 10 ns − 2 ns = 8 ns
Summary
- Faster rise time means higher speed operation
- Slower rise time can cause signal distortion
- Very fast rise time may introduce noise and EMI