Skip to main content

Why Transmitted and Received Power are Calculated in dBm

 

Why Transmitted and Received Power are Calculated in dBm

What is dBm?

dBm means:

  • dB relative to
  • 1 milliwatt (mW)
P(dBm) = 10 log₁₀(P(mW))
    

Examples:

Power dBm
1 mW 0 dBm
10 mW 10 dBm
100 mW 20 dBm
1000 mW (1 W) 30 dBm

Why Wireless Engineers Use dBm

In RF communication, signals experience:

  • Transmitter power
  • Antenna gain
  • Cable loss
  • Free-space path loss
  • Fading losses

Using linear watts would require lots of multiplication and division.

In dB form:

  • Multiplication becomes addition
  • Division becomes subtraction

Example Link Budget

Suppose:

  • Transmit power = 30 dBm
  • TX antenna gain = 15 dBi
  • Path loss = 103 dB
  • RX antenna gain = 10 dBi
Received Power = 30 + 15 - 103 + 10
               = -48 dBm
    

This is much easier than multiplying and dividing very large or very small numbers.

Another Example

For a single-mode optical fiber cable with an attenuation of 0.25 dB/km, the optical power (in dBm) at a distance of 100 km from a 0.1 mW light source is:

  • A. -10 dBm
  • B. -25 dBm
  • C. -30 dBm
  • D. -35 dBm
Solution:
Power of the light source:
0.1 mW = 10 log10(0.1) = -10 dBm
Optical power loss over 100 km:
Loss = 0.25 × 100 = 25 dB
Received optical power:
Preceiver = -10 - 25 = -35 dBm

Why Not Use Watts Directly?

Wireless signals can vary across extremely large ranges:

Signal Power
Cell tower Tens of watts
Phone receiver sensitivity Billionths of a watt

dBm compresses these huge ranges into manageable values.

Power dBm
20 W 43 dBm
0.000001 W -30 dBm
0.000000000001 W -90 dBm

Important Distinction Between dB Units

Unit Meaning
dB Ratio only
dBm Absolute power referenced to 1 mW
dBi Antenna gain relative to an isotropic antenna

This allows simple RF link-budget calculations:

  • Path loss → dB
  • Antenna gain → dBi
  • Transmit power → dBm


Contact Us

Name

Email *

Message *

Popular Posts

UGC NET Electronic Science Previous Year Question Papers with Solutions

Download Papers and Solutions Exam Pattern Preparation Tips FAQs More Home / Engineering & Other Exams / UGC NET 2026 PYQ 📊 Exam Highlights: Electronic Science (88) Feature Details Junior Research Fellowship (JRF) ₹37,000 + HRA per month Eligibility M.Sc/M.Tech in Electronics (55%) Validity of Certificate JRF (3 Years) | Lectureship (Lifetime) 📥 Download UGC NET Electronics PDFs Complete collection of previous year question papers, answer keys and explanations for Subject Code 88. Start Downloading 📂 View All Question Papers June 2026 - Question Paper Download PDF June 202...

Online Simulator for ASK, FSK, and PSK Signal Generation

Interactive Digital Signal Processing (DSP) Tutorial and Simulator for ASK, FSK, and BPSK modulation techniques. Try our new Digital Signal Processing Simulator!   •   Interactive ASK, FSK, and BPSK tools updated for 2025. Start Now Digital Modulation Visualizer: ASK, FSK, & BPSK Simulator Learn and visualize binary modulation techniques (ASK, FSK, BPSK) in real-time with adjustable carrier and sampling parameters. Perfect for DSP students and engineers. 📡 ASK Simulator 📶 FSK Simulator 🎚️ BPSK Simulator 📚 More Topics ASK Modulator FSK Modulator BPSK Modulator Demodulation More Topics 1. ASK (Ampli...

Linear vs Circular Convolution

Linear vs Circular Convolution Linear convolution vs circular convolution Linear convolution (what nature does) If: x[n] = transmitted signal h[n] = channel impulse response (multipath) Then the received signal is: y[n] = x[n] * h[n] This means: Past symbols spill into future symbols Causes inter-symbol interference (ISI) DFT of y[n] is not a simple product Circular convolution (what DFT assumes) The DFT assumes periodic signals : y[n] = x[n] ⊛ h[n], where indices wrap around modulo N Only under circular convolution does the DFT satisfy: Y[k] = X[k] · H[k] This is what enables one-tap frequency-domain equalization . What happens in the real channel (linear convolution) The channel performs linear convolution: y[n] = Σ l=0 Lh−1 h[l] x[n-l] But because: CP absorbs the “spillover” Receiver discards CP before DFT The useful part of the received symbol becomes: y[n] = Σ l=0 Lh−1 h[l] x[(n-l) mod N] Modulo inde...

Flat vs Frequency Selective Online Simulator

Flat vs Frequency Selective Online Simulator Channel Type Without Fading Flat Fading Multipaths Nakagami m SNR(dB) Run Simulation Input Signal Signal After Fading Constellation Diagram BER vs SNR Explore Advanced Flat vs Frequency-Selective Fading Simulator Want to see these equations in action? Visualize it. Launch Simulator Tool Interactive Rayleigh Fading Simulator Want to see Rayleigh fading in action? Visualize it. Launch Simulator Tool Return to DSP Simulations Main Page →

Theoretical BER vs SNR for binary ASK, FSK, and PSK (with MATLAB Code + Simulator)

📘 Overview & Theory 🧮 MATLAB Codes 🧮 Q-function 📚 Further Reading Bit Error Rate (BER) Equations In ASK, noise directly affects the signal amplitude, making it the most vulnerable since the data is carried in amplitude changes. In FSK, data is represented by frequency variations, and because noise typically impacts amplitude more than frequency, FSK is more robust than ASK. In PSK, data is encoded in the signal phase, and BPSK specifically uses 180-degree phase shifts, creating the greatest separation between signal points and therefore achieving the lowest bit error rate (BER) for the same power level. BER formulas for ASK, FSK, and PSK modulation schemes. ASK BER = 0.5 × erfc(0.5 × √SNR) FSK BER = 0.5 × erfc(√(SNR / 2)) PSK BER = 0.5 × erfc(√SNR) ...

CMOS Logic Gates: Inverter, NAND, and NOR

CMOS Logic Gates: Inverter, NAND, and NOR Complementary metal–oxide–semiconductor (CMOS) technology forms the backbone of modern digital IC design. Patented by Frank Wanlass in 1963 ( US patent 3,356,858 ), CMOS enables low-power, high-speed, and noise-immune logic circuits. CMOS gates, including inverters, NAND, and NOR, are widely used in both large-scale and small-scale integrated circuits due to their efficiency and versatility. CMOS Inverter A CMOS inverter consists of a complementary pair of PMOS and NMOS transistors. The PMOS transistor connects to the supply voltage V DD , while the NMOS connects to ground. The input voltage V IN controls both gates, and the output voltage V OUT is taken from the connected drains. CMOS inverters are highly energy-efficient and produce minimal heat due to their comple...

Design of CMOS XOR/XNOR Gates

Design of CMOS XOR/XNOR Gates The semiconductor industry has experienced rapid integration of multimedia applications into mobile electronics, leading to very high integration density in CMOS VLSI. As operating frequencies increase, power consumption, speed, silicon area, and reliability become critical considerations. The XOR-XNOR circuits are fundamental building blocks in arithmetic circuits (Full Adders, Multipliers), compressors, comparators, parity checkers, code converters, error-detecting/correcting codes, and phase detectors. Their performance directly impacts the complex circuits they are used in. Design goals include full output voltage swing, low power consumption, reduced transistor count, minimal delay, and simultaneous non-skewed outputs. Static Logic (Static CMOS) Stat...