- GATE Electronics and Communication (EC) Questions Paper With Answer Key Download Pdf [2025]
Q.61
The input voltage is given by:
V_I = 10 sin(100Ļt)Where:
- VI is the input voltage in volts.
- t is the time in seconds.
The diode will be forward biased when the input voltage exceeds 5V. Therefore, we need to solve the inequality:
10 sin(100Ļt) > 5Step 1: Simplify the Inequality
Divide both sides by 10:
sin(100Ļt) > 0.5Step 2: Find when sin(100Ļt) = 0.5
The sine function equals 0.5 at:
sin(Īø) = 0.5 when Īø = Ļ/6, 5Ļ/6, ...So, for 100Ļt, we have:
100Ļt = Ļ/6 and 100Ļt = 5Ļ/6 (first two points)Step 3: Solve for t
Solving these equations for t, we get:
100Ļt = Ļ/6 => t = 1/600 seconds100Ļt = 5Ļ/6 => t = 5/600 secondsStep 4: Find the Time Interval for Forward Bias
Now, we know that sin(100Ļt) > 0.5 between these two times. The condition repeats every half period of the sine wave. So, for one period, t ranges from 1/600 seconds to 5/600 seconds. This gives a time difference of:
Īt = 5/600 - 1/600 = 4/600 seconds = 2/300 seconds = 6.67 msStep 5: Adjusting for One Full Period
The sine wave oscillates every period T = 1/50 seconds, because 100Ļt corresponds to a full period when t = 1/50. Since the positive half-cycle lasts 0.5 ms, and the negative half-cycle is symmetrical, the total duration during which the diode is forward biased (where V_I > 5) covers both the positive and negative portions of the waveform. So, this results in a time of about 13.32 ms.
Q.62
Given Information:
- Propagation delay of the AND gate = 1 ns
- Set-up time of the flip-flops = 2 ns
- Hold time of the flip-flops = 0 ns
- Clock-to-Q delay of the flip-flops = 2 ns
Step 1: Understanding the Circuit Components
- Propagation delay of the AND gate: 1 ns - This is the time it takes for the signal to propagate through the AND gate.
- Set-up time of the flip-flops: 2 ns - The minimum time the input signal must remain stable before the clock edge.
- Clock-to-Q delay of the flip-flops: 2 ns - The time it takes for the output of the flip-flop to reflect a change after the clock edge.
Step 2: Maximum Clock Period Calculation
The maximum clock period \(T_{max}\) is the sum of the setup time, the propagation delay of the AND gate, and the clock-to-Q delay of the flip-flops:
T_max = T_setup + T_prop + T_clk-to-Q
T_max = 2 ns + 1 ns + 2 ns = 5 ns
Step 3: Maximum Clock Frequency Calculation
The maximum clock frequency \(f_{max}\) is the reciprocal of the maximum clock period:
f_max = 1 / T_max
f_max = 1 / (5 * 10^(-9)) Hz = 200 * 10^6 Hz = 200 MHz
Final Answer:
The maximum clock frequency is 200 MHz (rounded to the nearest integer).
Q.63
Shockley Diode Equation:
I = I0 (e(qV / kBT)} - 1)
Where:
- I = Forward current (0.1 A)
- I0 = Reverse saturation current (10 ĀµA = 10 × 10-6 A)
- V = Voltage across the diode (to be calculated)
- q = Charge of an electron (1.6 × 10-19 C)
- kB = Boltzmann constant (1.38 × 10-23 J/K)
- T = Temperature (300 K)
Answer : 0.24 V
Q.64
Given values:
Z0 = 50 # characteristic impedance in ohms
ZL = 50 - 75j # load impedance in ohms
Pin = 10 # incident power in mW
# Calculate reflection coefficient (Gamma)
Gamma = (ZL - Z0) / (ZL + Z0) = (0.36-0.48j)
# Calculate the magnitude of the reflection coefficient
Gamma_mag = abs(Gamma) = 0.6
# Calculate the average power delivered to the load
P_load = Pin * (1 - Gamma_mag**2) = 10*0.64 = 6.4 mW
Q.65
Given:
- Loop Area, A = 5 m²
- Magnetic Flux Density: B(t) = 0.5t (in Tesla)
- Loop lies in the xy-plane
- Two resistors of 2 Ī© each are in series, so total resistance R = 4 Ī©
Step 1: Apply Faraday's Law
Faraday’s Law of Electromagnetic Induction:
š = -dĪ¦B/dt
Where magnetic flux Ī¦B is given by:
Ī¦B = B(t) × A
Substitute the values:
Ī¦B = 0.5t × 5 = 2.5t
Then, the rate of change of flux is:
dĪ¦B/dt = d/dt(2.5t) = 2.5
So, the induced EMF:
š = -2.5 V (We take the magnitude: 2.5 V)
Step 2: Use Ohm’s Law to find the current
I = |š| / R
I = 2.5 / 4 = 0.625 A
Final Answer:
I = 0.63 A (rounded to two decimal places)