In the given block diagram of the PLL circuit, the input reference frequency fin = 40 MHZ. What is the value of output frequency fout when the PLL is operating in locked state?

In the given block diagram of the PLL circuit, the input reference frequency fin = 40 MHZ. What is the value of output frequency fout when the PLL is operating in locked state?

• 1. 10 MHZ
• 2. 36 MHZ
• 3. 4 MHZ
• 4. 160 MHZ

Answer: Option (4)

Phase-Locked Loop (PLL) Locking Condition

In a PLL, the divided VCO output must match the input reference frequency for the PLL to remain in the locked state. The block diagram shows a "÷4 Counter", meaning the VCO output is divided by 4 before being fed back to the phase-frequency detector.

Therefore, the locking condition is f_in = f_out / 4
With the given input reference frequency f_in = 40 MHz,
The locked VCO output frequency must be four times this value:
f_out = 4 × 40 MHz = 160 MHz

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