Interactive Phase Locked Loop (PLL) Simulator

PLL TRACKER

REFERENCE FREQ 200 Hz

LOOP GAIN (K) 2.0

FILTER CUTOFF 0.10

VCO Freq: --
Phase Error: --

INPUT (BLUE) VS VCO (RED)

CONTROL VOLTAGE (LOOP ERROR)

PLL Mathematical Dynamics

A Phase-Locked Loop (PLL) is a closed-loop feedback control system. Its purpose is to continuously compare a reference signal with a locally generated signal and adjust the local oscillator until both signals have the same frequency and a constant phase relationship.

Fundamental Error Equation

θ_err(t) = θ_ref(t) − θ_vco(t)

This quantity is called the phase error. The PLL's objective is to drive this error toward zero (or a small constant value) through feedback.

The Three-Stage Process

1. Phase Detector (PD)

The phase detector compares the phase of the reference signal with the phase of the VCO output.

V_d(t) ≈ K_d sin(θ_err(t))

where:

• V_d = detector output voltage
• K_d = detector gain
• θ_err = phase difference

For small phase errors:

sin(θ_err) ≈ θ_err

Therefore:

V_d ≈ K_dθ_err

2. Loop Filter (LPF)

The detector output contains both useful information and high-frequency components. The loop filter removes unwanted components and creates a smooth control voltage.

In many DSP implementations, a simple Exponential Moving Average (EMA) filter is used:

V_c[n] = αV_d[n] + (1−α)V_c[n−1]

where:

• α = filter coefficient
• V_d = detector voltage
• V_c = control voltage

Larger α values produce faster tracking but can increase jitter. Smaller α values provide smoother operation but slower lock times.

3. Voltage Controlled Oscillator (VCO)

The filtered control voltage changes the oscillator frequency.

ω_vco = ω_free + K_vV_c

where:

• ω_free = free-running frequency
• K_v = VCO sensitivity
• V_c = control voltage

If the VCO is running too slowly, the control voltage increases, causing the VCO frequency to rise. If the VCO is too fast, the voltage decreases, slowing it down.

Closed-Loop Interpretation

Phase Error → Detector → Filter → VCO → Feedback

The PLL continuously repeats this cycle. Every correction reduces the difference between the reference signal and the oscillator output.

Lock Condition

A PLL is considered locked when the phase error becomes constant.

dθ_err/dt = 0

At lock:

• Reference frequency = VCO frequency
• Phase difference becomes constant
• Control voltage stabilizes
• The loop no longer needs large corrections

Simulator Parameter Mapping

Simulator Label	Math Symbol	Description
Reference Frequency	fref	Target frequency
Phase Error	θerr	Difference between phases
Detector Gain	Kd	Phase detector sensitivity
Filter Alpha	α	Loop filter coefficient
VCO Gain	Kv	Frequency sensitivity of VCO
Control Voltage	Vc	Correction signal
VCO Frequency	fvco	Current oscillator frequency

Lab Observation: If the reference frequency suddenly changes, the phase error spikes, the filter generates a correction voltage, and the VCO gradually moves toward the new frequency. This transient behavior is called acquisition or capture.

Key Concept: A PLL does not directly force frequencies to be equal. Instead, it continuously minimizes phase error. Frequency synchronization is a natural consequence of maintaining a constant phase relationship.