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Phase Locked Loop (PLL) Simulator 2 (with Counters in Feedback)


Modern PLL Synthesizer Lab
fin P.F.D Charge Pump Loop Filter V.C.O fout ÷ N Counter

Frequency Synthesizer PLL (Digital Type)

Unlocked
VCO OUTPUT (fout) --
FEEDBACK FREQ --
fin →
PFD
→
LPF
→
VCO
→ fout
↑ ───
÷ N Counter
─── ┘

PLL Frequency Synthesizer Analysis

Step 1: PFD Equilibrium

The PFD compares $f_{in}$ and the feedback signal $f_{fb}$. At lock:

fin = ffb
Step 2: Frequency Division

The signal $f_{out}$ passes through the ÷N counter before returning:

ffb = fout / N
Step 3: Final Synthesis Solution

Substituting Step 2 into Step 1:

fout = fin × N
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