Interrupt Vectors (8051)
Each interrupt source in the 8051 has a fixed memory location called an interrupt vector address. When an interrupt occurs, the CPU jumps to this address to execute the Interrupt Service Routine (ISR).
| Flag | Interrupt Source | Vector Address | Description |
|---|---|---|---|
| IE0 | External Interrupt 0 (INT0) | 0003H |
Triggered by an external signal on INT0 pin |
| TF0 | Timer 0 Overflow | 000BH |
Occurs when Timer 0 overflows |
| IE1 | External Interrupt 1 (INT1) | 0013H |
Triggered by an external signal on INT1 pin |
| TF1 | Timer 1 Overflow | 001BH |
Occurs when Timer 1 overflows |
How It Works
- When an interrupt occurs, its corresponding flag (IE0, TF0, IE1, TF1) is set.
- If interrupts are enabled, the CPU finishes the current instruction.
- The program counter (PC) is pushed onto the stack.
- The CPU jumps to the corresponding vector address.
- The ISR is executed.
- After execution,
RETIreturns control to the main program.
Key Point
Flags (IE0, TF0, IE1, TF1) indicate that an interrupt has occurred, while vector addresses (0003H, 000BH, etc.) tell the CPU where to jump to handle that interrupt.