Skip to main content

What are the main lobe and side lobes in Beamforming

 

 What are the main lobe and side lobes in Beamforming?

You've probably noticed that in the diagram of beamforming, there are two types of lobes in beamforming patterns. One is the main lobe, while the others are side lobes. We intend to communicate with receivers with a stronger directional path from the transmitter when we produce beams for wireless communication. We can also see side lobes in this scenario. These side lobes, on the other hand, are not necessary for effective communication. As a result, we take various procedures to remove those side lobes or to reduce the number of side lobes as much as feasible; otherwise, inter-symbol interference occurs, and signal quality suffers.

Figure: Illustration of Main Lobe and Side lobes, where the x-axis denotes the angle of arrival (AOA) and angle of departure (AOD), respectively, while, the y-axis denotes the gain/power in dB (decibel).
   

In the case of MIMO antennas, our major goal is to reduce inter-symbol interface (ISI) by minimizing the number of side lobes, therefore we deploy antenna elements at half-wavelength intervals. It's a common practice to increase the power of the main lobe while reducing the power of the side lobes.


How to plot Main Lobes and Side lobes

The plotting of the main lobe and side lobes is not difficult. To begin, measure the received power at the receiver for a specific angle of arrival or departure (AOA/AOD).

For Example

At 28 GHz, UMi - LOS, 372-meter TX-RX Separation, Transmitted Power 30 dBm


The received power changes with parameters like the angle of arrival at the receiver, as seen in the example above.



We've plotted the graph of received power against the angle of arrival of the received signal in the diagram above. These are termed side lobes.

What causes the lobes to form?

Assume we have multiple transmitting antennas. Now, we gradually shift the phases of the antennas (using phase shifters (PSs) or manually), and the signal focuses on the resulting phase angles of those antennas.

 

Further Reading



Contact Us

Name

Email *

Message *

Popular Posts

LDPC Encoding and Decoding Techniques

Low Density Parity Check (LDPC) Guide Comprehensive analysis of linear error-correcting block codes, Tanner graphs, and 5G-NR implementations. ๐Ÿ“˜ Overview ๐Ÿงฎ Encoding ๐Ÿงฉ Decoding ๐Ÿ“š Resources Theory Encoding Tech Tanner Graph 5G Encoding Decoding 'LDPC' is the abbreviation for 'low density parity check'. LDPC code H matrix contains very few amount of 1's and mostly zeroes. LDPC codes are error correcting code. Using LDPC codes, channel capacities that are close to the theoretical Shannon limit can be achieved. Low density parity check (LDPC) codes are linear error-correcting block code suitable for error correction in a large block sizes transmi...

OFDM Symbols and Subcarriers Explained

This article explains how OFDM (Orthogonal Frequency Division Multiplexing) symbols and subcarriers work. It covers modulation, mapping symbols to subcarriers, subcarrier frequency spacing, IFFT synthesis, cyclic prefix, and transmission. Step 1: Modulation First, modulate the input bitstream. For example, with 16-QAM , each group of 4 bits maps to one QAM symbol. Suppose we generate a sequence of QAM symbols: s0, s1, s2, s3, s4, s5, …, s63 Step 2: Mapping Symbols to Subcarriers Assume N sub = 8 subcarriers. Each OFDM symbol in the frequency domain contains 8 QAM symbols (one per subcarrier): Mapping (example) OFDM symbol 1 → s0, s1, s2, s3, s4, s5, s6, s7 OFDM symbol 2 → s8, s9, s10, s11, s12, s13, s14, s15 … OFDM sym...

Online Simulator for ASK, FSK, and PSK Signal Generation

Interactive Digital Signal Processing (DSP) Tutorial and Simulator for ASK, FSK, and BPSK modulation techniques. Try our new Digital Signal Processing Simulator!   •   Interactive ASK, FSK, and BPSK tools updated for 2025. Start Now Digital Modulation Visualizer: ASK, FSK, & BPSK Simulator Learn and visualize binary modulation techniques (ASK, FSK, BPSK) in real-time with adjustable carrier and sampling parameters. Perfect for DSP students and engineers. ๐Ÿ“ก ASK Simulator ๐Ÿ“ถ FSK Simulator ๐ŸŽš️ BPSK Simulator ๐Ÿ“š More Topics ASK Modulator FSK Modulator BPSK Modulator Demodulation More Topics 1. ASK (Ampli...

Design of CMOS Flip-Flops (SR, D, JK)

Design of CMOS Flip-Flops (SR, D, JK) A flip-flop or latch is a circuit with two stable states, used to store state information. It is the basic storage element in sequential logic and a fundamental building block in digital electronics systems, including computers and communication devices. Flip-flops and latches act as data storage elements for states, pulse counting, and synchronization of variably-timed input signals to a reference clock. Flip-flops can be transparent/opaque (latches) or clocked (synchronous, edge-triggered). Latches are level-sensitive, while flip-flops are edge-sensitive. In sequential logic, the output depends on current inputs and previous states. Fig.1 shows a sequential circuit combining a combinational block and a memory element. ...

Flat vs Frequency Selective Online Simulator

Flat vs Frequency Selective Online Simulator Channel Type Without Fading Flat Fading Multipaths Nakagami m SNR(dB) Run Simulation Input Signal Signal After Fading Constellation Diagram BER vs SNR Explore Advanced Flat vs Frequency-Selective Fading Simulator Want to see these equations in action? Visualize it. Launch Simulator Tool Interactive Rayleigh Fading Simulator Want to see Rayleigh fading in action? Visualize it. Launch Simulator Tool Return to DSP Simulations Main Page →

Online Simulator for Frequency Modulatiuon and Demodulation

FM Modulation Simulator Frequency Modulation (FM) In Frequency Modulation, the frequency of the carrier signal varies in accordance with the message signal's amplitude. s FM (t) = A c cos(ฯ‰ c t + k f ∫m(t)dt) where ฯ‰ = 2ฯ€f & k f = Frequency Sensitivity Modulation index, ฮฒ = (k f * A m ) / f m Change the parameter values to see the effect. Message Freq (Hz) 1 Carrier Freq (Hz) Message Amplitude (Am) Kf (sensitivity): 50 Perform FM Demodulation ๐Ÿงช Experiment for Students: ...

UGC NET Electronic Science Previous Year Question Papers with Solutions

Download Papers and Solutions Exam Pattern Preparation Tips FAQs More Home / Engineering & Other Exams / UGC NET 2026 PYQ ๐Ÿ“Š Exam Highlights: Electronic Science (88) Feature Details Junior Research Fellowship (JRF) ₹37,000 + HRA per month Eligibility M.Sc/M.Tech in Electronics (55%) Validity of Certificate JRF (3 Years) | Lectureship (Lifetime) ๐Ÿ“ฅ Download UGC NET Electronics PDFs Complete collection of previous year question papers, answer keys and explanations for Subject Code 88. Start Downloading ๐Ÿ“‚ View All Question Papers June 2026 - Question Paper Download PDF June 202...